W631GG6KB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
CKE
ODT
DRAM_RTT
AL = 3
ODTH4min
ODTLon = CWL + AL - 2
t AONmin
AL = 3
ODTLoff = CWL + AL - 2
Rtt_Nom
CWL - 2
t AOFmin
t AONmax
t AOFmax
TRANSITIONING
Figure 74 – Synchronous ODT Timing (AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
CKE
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTH4
ODTH4min
ODTH4
ODT
ODTLoff = WL - 2
ODTLoff = WL - 2
ODTLon = WL - 2
ODTLon = WL - 2
t AONmin
t AOFmin
t AONmax
t AOFmin
DRAM_RTT
t AONmax
Rtt_Nom
t AONmin
t AOFmax
TRANSITIONING
t AOFmax
DON'T CARE
Figure 75 – Synchronous ODT (BL = 4, WL = 7)
Publication Release Date: Dec. 09, 2013
Revision A05
- 81 -
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